RESUME OF MICHAEL E. FISHER	598 Camino De La Cima San Marcos, Ca. 92069 Phone(HM) 619-744-7697 email: mfisher@sdcoe.k12.ca.us
Education: MSEE, University of Southern California BSEE, Washington University UCLA Extension courses, 24 units Hughes Masters Fellow Washington University Scholar

Background:
Recent experience in cable and satellite communications includes development of demodulation schemes, matched filtering, convolutional encoding and decoding, link budget and BER analysis, and GSM over satellite. Specific accomplishments in part include the designs for an acoustic processor, forward error correction per ITU standards, a burst TDMA modem, software based Costas Loop, RLS demodulation algorithm, display and control systems based upon distributed processor architecture's, and radar timing subsystems. Have performed the design, simulation, and testing of digital signal processing (DSP) algorithms using DADiSPTM, MatlabTM, Signal Processing Workbench (SPW), assembly code, 'C', some C++, and hardware including FPGAs. Have designed digital hardware for control, display, and processing subsystems. Have architected subsystems using RISC and SPARC single board computers on VME bus. Areas of familiarity include the design of analog audio, display deflection, and RF circuitry, and the use of UNIX based work stations. Systems engineering background includes the analysis and specification of requirements, and the development of system architecture's.

Graduate studies included probability theory, stochastic processes, continuous and discrete transform theory, mathematical pattern recognition, digital signal processing, and image processing. Self directed studies have included coding theory, digital communications, satellite communications in the area of quadrature demodulation schemes (phase, frequency, and data recovery), and DAMA network control schemes.

Firmware/Software Design experience includes the programming of digital signal processing functions (transversal filters, FFTs, matched filters, convolutional coding), radar timing subsystem control software, torpedo and cruise missile data interface routines, and DSP display routines for acoustic processing. Have written 'C' programs for Costa Loop and recursive least square (RLS) demodulation algorithms for narrow band TDMA, and trellis coded modulation/demodulation per the ITU-T (J.83) cable modem specification. These routines were primarily written in micro-code, assembly code, or 'C'. Have used DADiSPTM, MatlabTM, Cadence's Signal Processing Workbench (SPW), and HP's Omnisys for DSP analysis and development.

Hardware Design experience includes the design of computer peripherals, bit mapped CRT display memory including waterfall display control, applications using micro and bit slice processors, programmable state machines, and VME based subsystems. Have implemented DSP algorithms in FPGAs using graphic and VHDL design entry methods. Module level designs have employed ASIC, CMOS, FPGA, and TTL devices. System level designs have employed distributed processor architecture's. Although primarily digital, my experience includes the design of transconductance amplifiers, FET and bipolar circuitry, multistable circuitry, RF amplifiers, differential amplifiers, D/A circuitry, and circuitry for tone pulse modulation for proportional control.

Systems Engineering experience includes all phases of system development including proposal writing, concept development, analysis of requirements, specification of requirements, hardware and software architectural design, test, integration, and formal system testing. Have experience in digital signal processing related to undersea acoustics, satellite communications, and radar. Have architected or contributed significantly to the designs for a satellite communication terminal, radar processing subsystem, digital compression system (DCME), and missile launching systems. Have used computer modeling to predict the performance of firmware and software on distributed processor architecture's. Use various computer simulation applications (DADiSPTM, MatlabTM, and Cadence's SPW);


Experience:

TV/COMM INTERNATIONAL- (November 1996 to present) Sr. Staff Engineer, Systems. Cable Modem Development to ITU-T Annex-B / IEEE 802.14 Standards:
*	As a precursor to ASIC development, developed C/C++ FEC model including trellis encoding and decoding, Reed Solomon forward error detection and correction, randomization, interleaving, and frame synchronization. Trellis coding included differential precoding, ½ rate convolutional encoding, and QAM mapping. Trellis decoding included QAM unmapping, Viterbi, and differential decoding. Integrated FEC model with a QAM transmitter / receiver model for purposes of bit error testing.
*	Developed specification for an MMDS headend based upon use of modified TV/COM ASICs to perform transcoding functions
Conditional Access, MPEG2, System Related:
*	Developed system specification for a European cable headend and cable network, including conditional access, MPEG, modulation, demodulation, network management, and set top box requirements.
*	Developed specification for addressable control messages (ACMs), related to entitlement and control messages
*	Wrote specification for switching control over subsystem redundancy
*	Supported testing and debugging of transport scrambler subsystem
MARTIN MARIETTA - (August 1992 to October 1996) Engineer/Senior Scientific. Satellite Communications:
*	System architect for commercial satellite modem, matched filtering, modulator, and demodulator DSP
*	System architect for commercial DCME equipment design, hardware, and DSP processing
*	Developed digital signal processing designs for both non-burst (Costas) and burst (RLS) QPSK modem schemes written in MatLab and 'C' respectively. Used Signal Processing Workbench (SPW) to evaluate RLS fixed precision arithmetic performance, Synergy to take RLS down to Altera's FLEX10K-50 gate array
*	Investigated DSP techniques for broadband polyphase channelization and clock recovery (fred harris).
*	Performed satellite link analysis
*	Investigated low cost baseband architectures for satellite terminal, packet switched data transfer protocols (ATM, Frame Relay,SONET), and voice compression (CELP, MELP)
*	Wrote detailed VSAT specification including baseband processing, transceiver, and network control and network management functions.
*	Familiarity with telephony interfaces, network control and signalling schemes, vocoder technology, Erlang availability analysis (Excel spreadsheet)
*	Familiarity with FDMA (SCPC), NBTDMA, CDMA, CAMA network access
*	NBTDMA VSAT development working with GE's Corporate Research & Development
Autonomous Piloting and Landing System:
*	Designed the radar frequency and timing control subsystem, hardware, software, and RAM based programmable state sequencer with a workstation interface, VMIC2533 (VME to digital I/O)
Radar Systems:
*	Designed VME architecture's for real-time CFAR processing (DSP) of radar imagery
*	Designed a programmable radar timing generator (hardware & software) with VMIC2533 (VME to digital I/O) for interface to controlling workstation
*	Software I/F to Waveform Generator (RS232 USART)
*	Architected a real-time VME, Sharp LH9124, based system for processing CFAR radar data
*	Resurrected an X-band radar system including Martin Marietta proprietary array processors, 1 GB cache memory record system, and transputer I/O control.
McDONNELL DOUGLAS TECHNOLOGIES INC - (December 1991 to July 1992) Sr. Technical Specialist. I was the principal investigator for a product development effort performed under independent research and development (IRAD) funding. Incorporated real-time frequency domain convolution and a 125 MHz sampling scheme into a sophisticated RF radar target generator. These schemes were based upon using a single board computer (Array Microsystems a66540), and fast sample and delay memory designed with emitter coupled logic (ECL). Performed the front-end requirements analysis with the assistance of DADiSP (software math application), conceived the system design, and wrote the software required. Participated in customer presentations and proposal writing. Published article for Microwave Journal and a paper for the April 1993 IEEE radar conference.
ORINCON - (November 1989 to November 1991) Sr. Principle Engineer. I was responsible for the development of a VME system for hosting nontraditional signal processing (Multi-spectra, Neural Network Classifiers, other). The VME system hosts an expert classifier, a multi-hypothesis tracker, and operator and graphic display interfaces. In this capacity, I have performed systems engineering functions and technical supervision. The VME system is a real-time, multichannel, VxWorks based system hosted on Intel i860, i960, and Sun SPARC processors. Participated in proposal writing.
PREVIOUS ASSOCIATIONS - (Hughes, Scientific Atlanta, Interstate Electronics) (1971 -1989) Sr. Systems Engineer / Design Engineer. Performed both program and technical management functions, applications support for business development, and proposal writing, which was preceded by several years as a digital design engineer. Past assignments have included sizing firmware lines of code, modeling program performance in FORTRAN, design of firmware architecture, design of hardware architecture, and coding PASCAL or assembly level programs. Was a principal contributor to the concept development and design of a large distributed processor architecture having over 20 Motorola and Intel embedded processors that was developed for the US Navy. Was responsible for developing major portions of the design and performance specifications for this system as well. Engineering assignments at Hughes included the design of several data storage, control, and transmission subsystems. These subsystems included a telecommunications data link, digital to proportional pulse control, digital to tone, and digital to analog signal encoding circuitry. Influenced the design and test of subsystems designed by other engineers including circuit modules for multistate control, circuit continuity monitoring, tone control, servo/synchro conversion, and computer interface functions. Although my assignments were primarily digital, I specified analog interface requirements and occasionally performed the design of analog support circuitry using discrete transistors and operational amplifiers. Wrote firmware for the prototype development of programmable display technology that was designed around the Hughes 1632 microprocessor, which is based on AMD 2900 ALUs. Was solely responsible for design, code, and testing of this program. Was one of two engineers responsible for the display hardware design including RAM for data / instructions, ROM for program memory, memory access priority logic, I/O flag structure, and the CRT and computer interfaces. I designed a display memory (dynamic RAM) for the Frequency Analysis System (FAS-1a FFT signal processor at Interstate Electronics. Additionally, I designed the display refresh logic and the analog deflection circuitry for its CRT display. Following the hardware design, I wrote the firmware for controlling its display, quantizing data, frequency translation, background whitening, and the interpolating and decimating transversal filtering. I designed a DMA controller that supported pipelined processing, for an Interstate Electronics' prototype FFT processor . The FFT processor was comprised of two 88 bit, AMD 2900 type, bit slice processors. I also wrote firmware for the FIR filters employed in this design. This processor provided signal enhancement for LOFARgram analysis. I also designed a frequency synthesizer, record/playback amplifier using a low noise FET front end for playback, and tone detect and decode logic.
PERSONAL I.E.E.E. Member 08667594 Amateur radio, Extra Class (WB6BVR) Pilot, instrument rated Commercial Radio Telephone License (General/First Class PG-11-32963)

Glossary:

ALU	- Arithmetic Logic Unit
ATM	- Asynchronous Transfer Mode, packet based communications standard
ASIC	- Application Specific Integrated Circuit
BER	- Bit Error Rate
CELP	- Code Excited Linear Prediction
CAMA	- Coded Algorithm for Multiple Access
CDMA	- Code Division Multiple Access
CFAR	- Constant False Alarm Rate
CRT	- Cathode Ray Tube
D/A	- Digital to Analog
DAMA	- Demand Assignment Multiple Access
DCME	- Digital Circuit Multiplication Equipment
DMA	- Direct Memory Access
FDMA	- Frequency Division Multiple Access
FEC	- Forward Error Correction
FET	- Field Effect Transistor
FFT	- Fast Fourier Transform
FIR	- Finite Impulse Response filter (transversal filter)
FORTRAN	- Formula Translator, programming language
FPGA	- Field Programmable Gate Array
GSM	- Group Special Mobile, European cellular communications standard
GB	- Giga Byte
IEEE	- Institute of Electrical and Electronics Engineers, Inc.
I/O	- Input/Output
ITU	- International Telecommunication Union
LMDS	- Local Multipoint Distribution Service
LOFAR	- Low Frequency Acoustic Ranging, passive sonar processing
MELP	- Multi Excitation Linear Prediction
MHz	- Mega Hertz
MPEG	- Moving Picture Expert Group, digital video compression standard
MMDS	- Multichannel Multipoint Distribution System
NBTDMA	- Narrowband Time Division Multiple Access
QAM	- Quaternary Amplitude Modulation
QPSK	- Quaternary Phase Shift Keying
RAM	- Random Access Memory
RF	- Radio Frequency
RISC	- Reduced Instruction Set Computer
RLS	- Recursive Least Square
ROM	- Read Only Memory
SCPC	- Single Channel Per Carrier
SONET	- High speed fiber optic communication protocol
SPARC	- Scalable Processor Architecture
SPW	- Signal Processing Workbench
TTL	- Transistor Transistor Logic
USART	- Universal Synchronous / Asynchronous Transceiver
VHDL	- Verilog High Level Design Language
VME	- European standard for Eurocard Modules
VSAT	- Very Small Aperture satellite Terminal